1. Field of the Invention
The present invention relates to a semiconductor chip assembly, and more is particularly to a semiconductor chip assembly that includes a semiconductor chip, a conductive trace and a substrate and its method of manufacture.
2. Description of the Related Art
Semiconductor chips have input/output pads that must be connected to external circuitry in order to function as part of an electronic system. The connection media is typically an array of metallic leads (e.g., a lead frame) or a support circuit (e.g., a substrate), although the connection can be made directly to a circuit panel (e.g., a mother board). Several connection techniques are widely used. These include wire bonding, tape automated bonding (TAB) and flip-chip bonding.
Wire bonding is by far the most common and economical connection technique. In this approach, wires are bonded, one at a time, from the chip to external circuitry by thermocompression, thermosonic or ultrasonic processes. In thermocompression bonding, fine gold wire is fed from a spool through a clamp and a capillary. A thermal source is swept past an end of the wire to form a wire ball that protrudes from the capillary. The chip or capillary is then heated to about 200 to 300° C., the capillary is brought down over an aluminum pad, the capillary exerts pressure on the wire ball, and the wire ball forms a ball bond on the pad. The capillary is then raised and moved to a terminal on the support circuit, the capillary is brought down again, and the combination of force and temperature forms a wedge bond between the wire and the terminal. Thus, the connection between the pad and the terminal includes the ball bond (which only contacts the pad), the wedge bond (which only contacts the terminal) and the wire between the bonds. After raising the capillary again, the wire is ripped from the wedge bond, the thermal source is swept past the wire to form a new wire ball, and the process is repeated for other pads on the chip. Thermosonic bonding is similar to thermocompression bonding but adds ultrasonic vibration as the ball and wedge bonds are formed so that less heat is necessary. Ultrasonic bonding uses aluminum wire to form wedge bonds without applying heat. There are many variations on these basic methods.
TAB involves bonding gold-bumped pads on the chip to external circuitry on a polymer tape using thermocompression bonding. TAB requires mechanical force such as pressure or a burst of ultrasonic vibration and elevated temperature to accomplish metallurgical welding between the wires or bumps and the designated surface.
Flip-chip bonding involves providing pre-formed solder bumps on the pads, flipping the chip so that the pads face down and are aligned with and contact matching bond sites, and melting the solder bumps to wet the pads and the bond sites. After the solder reflows it is cooled down and solidified to form solder joints between the pads and the bond sites. Organic conductive adhesive bumps with conductive fillers in polymer binders have been used in place of solder bumps, but they do not normally form a metallurgical interface in the classical sense. A major advantage of flip-chip bonding over wiring bonding and TAB is that it provides shorter connection paths between the chip and the external circuitry, and therefore has better electrical characteristics such as less inductive noise, cross-talk, propagation delay and waveform distortion. In addition, flip-chip bonding requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space are used.
While flip-chip technology has tremendous advantages over wire bonding and TAB, its cost and technical limitations are significant. For instance, the cost of forming bumps on the pads is significant. In addition, an adhesive is normally underfilled between the chip and the support circuit to reduce stress on the solder joints due to thermal mismatch between the chip and the support circuit, and the underfilling process increases both manufacturing complexity and cost. Furthermore, the solder joints exhibit increased electrical resistance as well as cracks and voids over time due to fatigue from thermo-mechanical stresses. Finally, the solder is typically a tin-lead alloy and lead-based materials are becoming far less popular due to environmental concerns over disposing of toxic materials and leaching of toxic materials into ground water supplies.
Other techniques besides wire bonding, TAB and flip-chip bonding have been developed to connect chips to external circuitry without using wires, leads or bumps. Such techniques include thin film rerouting at the wafer, panel or module level, and attaching a pre-patterned substrate to the chip such that through-holes in the substrate expose the pads and selectively applying conductive material into the through-holes.
A typical thin film routing approach includes depositing a dielectric material on the chip, providing through-holes in the dielectric material that expose the pads, providing metallization in the through-holes that contacts the pads, and providing a top layer of conductive circuitry on the dielectric material that contacts the metallization. In this manner, the additional circuitry is fabricated on the chip. Drawbacks to this approach include complicated manufacturing requirements, high cost, and chip loss if the additional circuitry is defective. In particular, since the chip or wafer provides a substrate for the additional circuitry, chips will be lost if the additional circuitry fails to achieve certain quality and yield criteria. Unpredictable chip loss has prevented the wide spread adoption of this “chip first” approach in volume production. Furthermore, if the process is not performed on wafers, the commercially available silicon wafer processing equipment may not be compatible with common tooling and handling techniques.
Chip scale packages (CSP) have emerged as a popular packaging technique for memory chips such as static random access memory (SRAM), dynamic random access memory (DRAM) and flash memory as well as other chips with low pin counts. Chip scale packages are hardly larger than the chip itself. However, advanced logic chips such as microprocessors, digital signal processors (DSP) and application-specific integrated circuits (ASIC) often require the package to be considerably larger than the chip to accommodate high pin counts and meet motherboard pitch limitations.
Unfortunately, these larger packages often employ wire bonding, TAB or flip-chip bonding, and as mentioned above, these connection techniques are not entirely satisfactory.
Bumpless Build-Up Layer (BBUL) is a package developed by Intel Corporation for advanced logic chips. The BBUL package includes a chip embedded in a substrate, such as bismaleimide triazine laminate or a copper heat spreader, which then has one or more build-up layers sequentially formed on the chip-substrate assembly. The substrate provides additional area to accommodate larger structures.
The BBUL manufacturing process includes punching a hole in a substrate, applying tape on the substrate to seal the hole at one end, disposing a chip in the hole such that the chip is coplanar with the substrate and the pads contact the tape, depositing an encapsulant in the hole and curing the encapsulant, removing the tape thereby exposing the pads, cleaning the pads, laminating a first dielectric layer on the chip and the substrate where the tape was previously located, laser drilling vias in the first dielectric layer that expose the pads, depositing and patterning metal by a semi-additive process such that the metal extends through the vias and contacts the pads, repeating the dielectric layer laminating, laser drilling and metal depositing and patterning for additional layers, depositing a photoimageable solder mask on the final layer, screen printing presolder in the solder mask, and attaching pins and land-side capacitors by a surface mount process. Thus, the BBUL package is one-sided and there are no plated through-holes or back-side wiring layers.
The BBUL package has the advantages of small electrical loop inductance, reduced thermomechanical stress, high lead count, component integration, and scalability. However, the BBUL package has the disadvantages mentioned above for thin film routing. Namely, complicated manufacturing requirements, high cost, and chip loss if the additional circuitry is defective. Furthermore, the BBUL package does not route the pads to the back-side of the substrate.
In view of the various development stages and limitations in currently available semiconductor chip assemblies, there is a need for a semiconductor chip assembly that is cost-effective, reliable, manufacturable, provides excellent mechanical and electrical performance, and is well-suited for advanced logic chips with high pin counts.